1 Field of the Invention
This invention relates to a chip scale package, and more specifically to a package body for use in encapsulating a semiconductor chip disposed on a substrate.
2. Description of the Related Art
FIGS. 1-3 illustrates three prior art chip scale packages. Typically a chip scale package comprises a semiconductor chip 110 disposed on the upper surface of a substrate 130 through an elastomer 120, and a package body 150 for providing environmental sealing and electrical insulation for the semiconductor chip 110. The package body 150 generally comprises a single layer structure formed of epoxy based material.
Normally, the semiconductor chip is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm .degree. C..sup.-1 and the substrate is usually formed of polymer having a coefficient of thermal expansion of 20-30 ppm .degree. C..sup.-1. Since there is a significant difference between the semiconductor chip 110 and the substrate 130 in CTE, the semiconductor chip 110 and the substrate 130 expand and contract in different amounts along with temperature fluctuations. This imposes both shear and bend stresses on the package body 150. Moreover, due to the flexible nature of the substrate, the substrate tends to warp or bend during packaging process and temperature fluctuations. This greatly magnifies the problems associated with the destructive stresses imposed on the package body 150. And when the warpaged chip scale package is subject to pressure cook test (PCT) or other reliability tests, problems of peeling, delaminatoin or die cracking easily occur.